Semiconductor device having a metal silicide layer and method for manufacturing the same

ABSTRACT

The present invention provides a semiconductor device having a metal silicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod for manufacturing the same. More particularly, the presentinvention relates to a semiconductor device which is formed with a lowresistance metal silicide layer having a superior phase stability and toa method for manufacturing the metal silicide layer.

[0003] 2. Description of the Related Art

[0004] As semiconductor devices become more highly integrated, thedesign rule of a device, such as channel length, an interval between theactive areas, a wiring width, a wiring interval, and a contact size of atransistor are scaled-down. Regarding the contact size of a transistor,a silicidation process for forming a metal silicide is carried out inorder to obtain a low resistance contact. Reducing the size of thecontact causes the thickness uniformity of a suicide layer and the stepcoverage of the silicide layer to be of inferior quality.

[0005] Conventionally, the metal silicide layer is formed on a bottom ofa contact hole or a via hole using an argon sputtering process and anevaporation process using an electronic beam. However, use of thoseprocesses results in less step coverage than if a CVD (chemical vapordeposition) process is used. Additionally, it is difficult to uniformlycontrol the thickness of the silicide layer.

[0006] When the metal silicide layer is formed using the CVD process,silicon etching can occur depending on the vacuum levels caused by thesource gas which is deposited at a high temperature. In addition, theisotropic deposition feature can cause undesired metal deposition atsidewalls of the contact hole or the via hole. Accordingly, the silicondeposited on the bottom of the contact hole reacts with the metaldeposited on the sidewalls of the contact hole. In this case, thesilicon is over-consumed, so bulk depletion and voids are generated,which cause contact resistance failure. In addition, the step coveragemay be reduced depending on the aspect ratio of the contact hole whenthe silicide layer is formed using the CVD process.

[0007] U.S. Pat. No. 5,780,929 discloses a method for forming a defectenhanced cobalt silicide layer. According to the disclosure of theabove-referenced U.S. patent, a silicon substrate is defected byimplanting argon into the silicon substrate without performing aseparate heat treatment process. However, it is difficult to defect thesilicon substrate properly, so the defection remaining on a surface ofthe silicon substrate can act as a source of current leakage. Inaddition, since the resistance is increased due to the argon implantedinto the silicon substrate, the resistance reducing effect of a shallowsilicide layer is reduced when a shallow junction is formed using theabove method.

[0008] On the other hand, as the design rule of the device is scaleddown, a margin is required with respect to a short channel effect and apunch-through of the transistor. Accordingly, forming a shallow junctionof a source/drain area and reducing the parasitic resistance, such as asheet resistance and a contact resistance, of the source/drain area arerequired. For this reason, a self-aligned silicide (hereinafter,referred to as “salicide”) process has been developed, in which thesilicide is selectively formed on a surface of a gate and a surface of asource/drain area to reduce the non-resistance of the gate, and thesheet resistance and contact resistance of the source/drain area.

[0009] According to a conventional salicide process, a metal layer isdeposited in a sputtering method. Then a first heat-treatment process iscarried out to form a metal silicide layer having a first phase.Non-reacted metal layers are selectively removed by a wet etchingprocess. Then, a second heat-treatment process is carried out to form ametal silicide layer having a second phase, which is stable with respectto the resistance and the phase stability as compared with the metalsilicide having the first phase. However, the conventional salicideprocess does not uniformly form a shallow silicide layer having athickness of less than 400 Å, which is problematic. When a silicidelayer having a thickness of greater than 400 Å is formed, the uniformityof thickness and the uniformity of the surface roughness are reduced.Furthermore, the distance between the junction portion and the silicidelayer is irregularly formed making it difficult to preserve thejunction. For example, if the salicide process is carried out afterdepositing a cobalt layer having a thickness of greater than 100 Å, thethickness difference of a cobalt disilicide layer (CoSi₂) having athickness of 300 to 400 Å is greater than ±150 Å. In addition, since theheat-treatment process is carried out twice, the high heat budget cancause the agglomeration of the metal silicide layer and lateralover-growing.

[0010] In order to solve the aforementioned problems, a process forforming an epitaxial silicide layer has been suggested. However, thisprocess requires a monocrystalline silicon seed and therefore, is notadapted for the polycrystalline silicon layer. In addition, the vacuumlevel of the process chamber has to be maintained below 1 E-10 torr inorder to obtain reproducibility. Furthermore, the deposition speed andthe throughput are reduced; hence, it is not adapted formass-production.

SUMMARY OF THE INVENTION

[0011] In order to solve the aforementioned problems, it is a feature ofan embodiment of the present invention to provide a semiconductor devicewhich achieves a low contact resistance by forming an ohmic contact withrespect to a semiconductor layer by using a metal silicide thin film.

[0012] Another feature of an embodiment of the present invention is toprovide a method for forming a low resistance metal silicide having ahigh phase stability by using native metal silicide formed at aninterfacial area between metal and silicon.

[0013] Still another feature of an embodiment of the present inventionis to provide a method for forming a metal silicide layer in asemiconductor device, in which a salicide process can be achieved byusing native metal silicide formed at an interfacial area between metaland silicon.

[0014] In an embodiment of the present invention, there is provided asemiconductor device having a metal silicide-semiconductor contactstructure, the semiconductor device comprising: a substrate; aninsulation layer having an opening formed on the substrate; a metalsilicide layer formed in the opening of the insulation layer, by using anative metal silicide having a first phase, the metal silicide layerhaving a second phase which has a first stoichiometrical compositionratio that is different from a second stoichiometrical composition ratioof the first phase; a conductive layer formed on the metal silicidelayer of the second phase, wherein the metal silicide layer is formedbetween the substrate and the conductive layer and the metal silicidelayer has a thickness of less than about 100 Å.

[0015] In another embodiment of the present invention, there is provideda method for forming a metal silicide layer in a semiconductor devicecomprising: i) providing a substrate; ii) forming an insulation layer onthe substrate, the insulation having an opening therein; iii) depositinga metal in the opening of the insulation layer so that a first layerincluding a native metal silicide layer of a first phase is formed at aninterfacial area between the substrate and the deposited metal; iv)selectively removing the first layer while retaining the native metalsilicide layer of the first phase; v) forming a second layer made of aconductive material on the native metal silicide layer of the firstphase and the insulation layer; and vi) reacting the native metalsilicide layer of the first phase with the substrate in order totransform the native metal silicide layer into a metal silicide layerhaving a second phase which has a first stoichiometrical compositionratio that is different from a second stoichiometrical composition ratioof the first phase.

[0016] In still another embodiment of the present invention, there is,provided a method for forming a metal silicide layer in a semiconductordevice comprising: i) providing a substrate having formed thereon a gateoxide film and a gate stack including a conductive material includingsilicon and having gate sidewall spacers on sides thereof; ii)depositing a metal on the substrate, the gate stack and the gatesidewall spacers, in such a manner that a first layer including a nativemetal silicide layer of a first phase is formed at an interfacial areabetween the silicon and the deposited refractory metal; iii) selectivelyremoving the first layer while retaining the native metal silicide layerof the first phase; iv) depositing a first capping layer on a resultingstructure; and v) reacting the native metal silicide layer of the firstphase with the silicon in order to transform the native metal silicidelayer into a metal silicide layer having a second phase which has afirst stoichiometrical composition ratio that is different from a secondstoichiometrical composition ratio of the first phase and a thickness ofless than about 100 Å.

[0017] According to yet another embodiment of the present invention, byusing the native metal silicide formed at an interfacial area betweenthe metal and the silicon, the native metal silicide layer is reactedwith the silicon by means of a heat-treatment process so that a metalsilicide layer with high phase stability and low resistance is obtained.Therefore, a thin metal suicide layer is uniformly formed, and thestepped portion is uniformly coated with the thin metal silicide layer.Additionally, when an embodiment of the present invention is applied tothe salicide process, the primary heat-treatment process can be skippedso that the heat budget is reduced. Accordingly, the process issimplified and a shallow junction may be achieved.

[0018] These and other features of the present invention will be readilyapparent to those of ordinary skill in the art upon review of thedetailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above features and other advantages of the present invention,as well as others, will become more apparent by describing in detailpreferred embodiments thereof with reference to the attached drawings inwhich:

[0020]FIG. 1 is a sectional view of a semiconductor device according toan embodiment of the present invention;

[0021]FIGS. 2A to 2D are sectional views of a semiconductor deviceillustrating a method for forming metal silicide according to a firstembodiment of the present invention;

[0022]FIGS. 3A to 3D are sectional views of a semiconductor deviceillustrating a method for forming metal silicide according to a secondembodiment of the present invention;

[0023]FIGS. 4A to 4C are sectional views of a semiconductor deviceillustrating a method for forming metal silicide according to a thirdembodiment of the present invention; and

[0024]FIGS. 5A to 5D are sectional views of a semiconductor deviceillustrating a method for forming metal silicide according to a fourthembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Korean Patent Application No. 2000-55769, filed on Sep. 22, 2000,and entitled: “Semiconductor Device Having a Metal Silicide Layer andMethod for Manufacturing the Same,” is incorporated by reference hereinin its entirety.

[0026] Hereinafter, preferred embodiments of the present invention willbe described in detail with reference to accompanying drawings.

[0027]FIG. 1 is a sectional view of a semiconductor device of anembodiment of the present invention.

[0028] Referring to FIG. 1, an insulation layer 12 is formed on asemiconductor substrate 10 that is comprised of silicon (Si), silicongermanium (SiGe), silicon-on-insulator (SOI), orsilicon-germanium-on-insulator (SGOI). The insulation layer 12 has anopening 14 for exposing a semiconductor area, such as a predeterminedarea of the semiconductor substrate 10. The semiconductor area is eitherthe semiconductor substrate 10 or a silicon layer or silicon germaniumlayer in the form of a crystalline phase or an amorphous phase formed onthe semiconductor substrate 10.

[0029] By using native metal silicide of a first phase, which is formedat an interfacial area between metal and silicon, a thin metal silicidelayer 16 is formed on the semiconductor area which is exposed by theopening 14. The thin metal silicide layer 16 has a second phase having afirst stoichiometrical composition ratio that is different from a secondstoichiometrical composition ratio of the first phase. A conductivelayer 18 is formed on the metal silicide layer 16 of the second phasethereby forming a metal silicide-semiconductor contact structure. Themetal silicide layer 16 has a thickness of less than about 100 Å and aresistance between about 3 to 20 Ω/□. The conductive layer 18 iscomprised of silicon or silicon germanium in the form of the crystallinephase or the amorphous phase. Preferably, the conductive layer 18 is asemiconductor layer comprised of doped polycrystalline silicon.

[0030] According to an embodiment of the present invention, in a contactstructure between semiconductor layers including the semiconductorsubstrate, a metal silicide layer is formed between the semiconductorlayers so that an ohmic contact is formed with respect to upper andlower semiconductor layers. In the conventional contact structure, aninterfacial characteristic is lowered due to a native oxide filmremaining on a surface of a lower semiconductor layer so that thecontact resistance is increased up to between about 2,000 and 10,000 Ω.The variation of the contact resistance is also increased. On thecontrary, an embodiment of the present invention forms the metalsilicide layer between the semiconductor layers, so not only is an ohmiccontact with respect to the upper and lower semiconductor layersachieved, but also the interfacial characteristic is improved since thenative oxide film formed on the surface of the lower semiconductor layeris replaced with silicide. Accordingly, the contact resistance of themetal silicide-semiconductor contact structure is reduced to less than1,000 Ω and the contact resistance is uniformly achieved.

[0031] Hereinafter, various embodiments of the present invention forforming a semiconductor device having a metal silicide layer will bedescribed with reference to the accompanying drawings.

First Embodiment of the Inventive Method

[0032]FIGS. 2A to 2D are sectional views of a semiconductor deviceillustrating a method for forming a metal suicide layer in asemiconductor device according to a first embodiment of the presentinvention.

[0033] Referring to FIG. 2A, a semiconductor substrate 100 comprisingsilicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), orsilicon-germanium-on-insulator (SGOI) is subject to an isolation processso that the semiconductor substrate 100 is divided into an active areaand a field area. Then, a gate oxide film 102 and a gate stack 106 areformed on the semiconductor substrate 100. Particularly, the gate oxidefilm 102 is grown by thermal oxidation, and a highly impurity-dopedpolycrystalline silicon layer 104 is deposited on the gate oxide film102. The polycrystalline silicon layer is doped by a conventional dopingprocess, such as a diffusing process, an ion implanting process, or anin-situ doping process. After depositing a mask layer 105 comprisingsilicon nitride on the polycrystalline silicon layer 104, a photoetching process is carried out for patterning the mask layer 105 and thepolycrystalline silicon layer 104, thereby forming the gate stack 106.The mask layer 105 increases the shoulder margin when the followingself-align contact process is carried out.

[0034] Next, gate sidewall spacers 108 comprising silicon nitride areformed at both sides of the gate stack 106 and a source/drain area 107is formed on the active area of the substrate 100 using an ionimplantation process.

[0035] Thereafter, an insulation layer 110 comprising silicon oxide isdeposited on an entire surface of the resulting structure. Then, theinsulation layer 100 is partially etched by an anisotropic etchingprocess having an etching selectivity between the silicon oxide film andthe silicon nitride film so that an opening 111 for exposing thesemiconductor area, that is, the source/drain area 107, is formed.

[0036] Referring to FIG. 2B, after performing a wet cleaning process forremoving the native oxide film and impurities remaining on a siliconsurface, an RF plasma etching for cleaning is carried out in RFsputtering equipment. Then, a first layer 112 of a metal (refractorymetals, novel metals, transition metals are included) which is oneselected from the group consisting of cobalt (Co), titanium (Ti),tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), and palladium(Pd) is deposited on the opening 111 and the insulation layer 110,in-situ, to a thickness of greater than 50 Å. As a result, asilicidation reaction between the metal and the silicon occurs at aninterfacial surface of the first layer 112 and the silicon area (thatis, source/drain area 107), so that a native metal silicide layer 114 ofthe first phase is formed to a thickness between about 25-35 Å. Inaddition, while the native metal silicide layer 114 is growing, theimpurities remaining at the interfacial surface of the metal and thesilicon are removed by the newly created suicide, and the interfacialsurface of the metal silicide and the silicon is buried below theinitial surface of the silicon area. As a result, a complete metalsilicide-silicon contact is formed.

[0037] For example, when cobalt is deposited on the silicon substrate toa thickness of 100 Å, a uniform native cobalt monosilicide (CoSi) isstably formed at an interfacial surface between the cobalt layer and thesilicon substrate.

[0038] Referring to FIG. 2C, the first layer 112 is selectively removedwhile retaining the native metal silicide layer 114 by a wet etchingprocess using a chemical having an etching selectivity with respect tothe first layer 112 and the metal silicide layer 114. Preferably, in thewet etching process, a pan strip is carried out at a temperature ofabout 65° C. for about 30 minutes without using H₂O₂, or a sulfuricstrip process is carried out at a temperature of about 145° C. for about20 minutes.

[0039] Referring to FIG. 2D, a second layer 116, preferably a dopedpolycrystalline silicon layer, is deposited on the metal silicide layer114 of the first phase and the insulation layer 110. The second layer116 comprises silicon or germanium in the form of a crystalline phase oran amorphous phase and is electrically connected to the source/drainarea 107 through the opening 111. Then, a rapid thermal process (RTP) iscarried out at a temperature of 850° C. for 30 seconds to cause areaction between the metal silicide layer 114 of the first phase and thesilicon thereby transforming the metal silicide layer 114 into a metalsilicide layer 115 having a second phase which has a firststoichiometrical composition ratio different from a secondstoichiometrical composition ratio of the first phase. For example, ifthe cobalt monosilicide (CoSi) having a, thickness of about 30 Å isheat-treated, the volume thereof is expanded, so that a cobaltdisilicide (CoSi₂) having a thickness of less than about 100 Å and asheet resistance of about 20 Ω/□ is formed.

[0040] In the present embodiment, the second layer 116 is depositedbefore the heat treatment process is carried out, so a predeterminedphase transition occurs in the metal silicide layer 114 of the firstphase by the heat budget when the deposition process is carried out. Atthis time, a silicon source for the phase transition is supplied fromboth the semiconductor substrate 100 and the second layer 116, so ashallow junction of the source/drain area can be achieved. Besides theheat-treatment process, various kinds of processes can be used to causea reaction between the metal silicide and the silicon.

[0041] Then, a chemical mechanical polishing (CMP) process is performedwith respect to the resulting structure formed with the metal silicidelayer 115 of the second phase, so that the second layer 116 is removeduntil the surface of the insulation layer 110 is exposed in such amanner that the second layer 116 remains only in the opening 111. As aresult, the contact structure consisting of second (polycrystallinesilicon) layer 116—silicide layer 115—semiconductor substrate (that is,source/drain area 107) is obtained. The metal silicide layer 115 acts asan ohmic contact with respect to upper and lower semiconductor layersand provides a low contact resistance. The second layer 116 can beformed in a plug shape as shown in FIG. 2D, or can be patterned with apredetermined pattern by means of a photo etching process. The secondlayer 116 reduces the aspect ratio of a contact hole formed thereon.

[0042] According to the first embodiment of the present invention, a lowresistance metal silicide having a high phase stability is formed byperforming the heat treatment process to the native metal silicide thinfilm which is uniformly formed at the interfacial area of the metal andthe silicon. Therefore, a thin metal silicide layer having a uniformthickness may be achieved. In the conventional sputtering method orchemical vapor deposition method for forming metal silicide, the stepdifference portions are unevenly coated and voids are created. However,the present invention solves the above problems by using an interfacialsilicide.

[0043] In addition, according to the first embodiment of the presentinvention, the contact resistance is reduced by forming an ohmic contactof metal silicide-semiconductor. Furthermore, since the semiconductorlayer is deposited before the heat treatment process for the phasetransition of metal silicide is carried out, a thin junction iseffectively achieved.

Second Embodiment of the Inventive Method

[0044]FIGS. 3A to 3D are sectional views of a semiconductor deviceshowing a method for forming a metal silicide layer in a semiconductordevice according to a second embodiment of the present invention.

[0045] Referring to FIG. 3A, a field oxide film 201 is formed on asemiconductor substrate 200 by means of an isolation process so that thesemiconductor substrate 200 is divided into an active area and a fieldarea. Then, a MOS transistor (not shown) is formed on the active area ofthe substrate 200 by using a MOS transistor manufacturing process.Thereafter, a first insulation layer (not shown) is deposited on the MOStransistor and the substrate 200. The first insulation layer is etchedby using a photo etching process thereby exposing the active area.

[0046] Next, a silicon or silicon germanium layer, such as a dopedpolycrystalline silicon layer, in the form of a crystalline phase or anamorphous phase, is deposited on an entire surface of the resultingstructure. A pad layer 202 which makes contact with the active area isformed by patterning the doped polycrystalline silicon layer. The padlayer 202 can be formed by means of a self-align contact process.

[0047] Thereafter, a second insulation layer 204 is deposited on the padlayer 202 and the substrate 200 and a bit line stack 206 is formed onthe second insulation layer 204 by using a bit line fabricating process.The bit line stack 206 is formed as a mono-layer of the dopedpolycrystalline silicon layer, or formed as a polycide structure of thedoped polycrystalline silicon layer and the metal silicide layer. Inaddition, the bit line stack 206 includes a bit line capping layer whichis made of an insulation material and is formed on the bit line stack206.

[0048] Then, after depositing a third insulation layer 208 on the bitline stack 206 and the second insulation layer 204, the third insulationlayer 208 is planarized by using a reflow process, an etch-back processor a CMP process. The third insulation layer 208 is partially etched byusing a photo etching process so that an opening 210 for exposing asemiconductor area, that is the pad layer 202, is formed. At this time,the opening 210 can be formed by means of a self-align contact process.

[0049] Referring to FIG. 3B, a first layer 212 of a metal which isselected from the group consisting of cobalt (Co), titanium (Ti),tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), and palladium(Pd) is deposited on the opening 210 and the third insulation layer 208to a thickness of greater than about 50 Å. As a result, a silicidationreaction between the metal and the silicon occurs at an interfacialsurface of the exposed pad layer 202 and the first layer 212, so that anative metal silicide layer 214 of the first phase is formed to athickness between about 25-35 Å. For example, when the cobalt isdeposited, a native cobalt monosilicide (CoSi) layer is formed at abottom portion of the opening 210 to a thickness of about 30 Å.

[0050] Referring to FIG. 3C, the first layer 212 is selectively removedwhile retaining the native metal suicide layer 214 of the first phase bya wet etching process using a chemical having an etching selectivitywith respect to the first layer 212 and the metal silicide layer 214.Preferably, in the wet etching process, a pan strip is carried out at atemperature of about 65° C. for about 30 minutes without using H₂O₂, ora sulfuric strip is carried out at a temperature of about 145° C. forabout 20 minutes.

[0051] Referring to FIG. 3D, a second layer 216 such as a dopedpolycrystalline silicon layer is deposited on the metal silicide layer214 of the first phase and the third insulation layer 208. The secondlayer 216 comprises silicon or germanium in the form of a crystallinephase or an amorphous phase and is electrically connected to the padlayer 202 through the opening 210. At this time, a predetermined phasetransition occurs in the metal silicide layer 214 of the first phase bythe heat budget when the deposition process is carried out.

[0052] Then, a rapid thermal process (RTP) is carried out at atemperature of about 850° C. for about 30 seconds to cause a reactionbetween the metal silicide layer 214 of the first phase and the silicon,thereby transforming the metal silicide layer 214 into a metal silicidelayer 215 having a second phase which has a first stoichiometricalcomposition ratio different from a second stoichiometrical compositionratio of the first phase. For example, if the cobalt monosilicide (CoSi)layer having a thickness of about 30 Å is heat-treated, the volumethereof is expanded, so that a cobalt disilicide (CoSi₂) layer having athickness of less than 100 Å and a sheet resistance of 20 Ω/□ is formed.

[0053] Thereafter, a chemical mechanical polishing (CMP) process isperformed to remove the polycrystalline silicon layer 216 such that thesurface of the third insulation layer 208 is exposed so that thepolycrystalline silicon layer 216 remains only in the opening 210. As aresult, the contact structure consisting of polycrystalline siliconlayer 216—metal silicide layer 215—pad layer 202 is obtained. The metalsilicide layer 215 acts as an ohmic contact with respect to upper andlower semiconductor layers. The polycrystalline silicon layer 216 can beformed in a plug shape as shown in FIG. 3D, or can be patterned with astorage electrode pattern by means of a photo etching process.

[0054] According to the second embodiment of the present invention, withthe replacement of the conventional semiconductor-semiconductorstructure with the inventive semiconductor-metal silicide-semiconductorohmic contact structure, interfacial feature is improved and the contactresistance is reduced.

Third Embodiment of the Inventive Method

[0055]FIGS. 4A to 4C are sectional views of a semiconductor deviceshowing a method for forming a metal silicide layer in a semiconductordevice according to a third embodiment of the present invention.

[0056] Referring to FIG. 4A, a device structure (not shown) is formed ona semiconductor substrate 300 consisting of silicon (Si), silicongermanium (SiGe) and silicon-on-insulator (SOI), orsilicon-germanium-on-insulator (SGOI). The device structure includes atransistor, a bit line and a capacitor.

[0057] Then an insulation layer 302 is deposited on the device structureand the substrate 300. Thereafter, the insulation layer 302 is etched toform a contact hole 303 for exposing a semiconductor area, such as apredetermined area of the semiconductor substrate 300. The semiconductorarea exposed through the contact hole 303 is either the semiconductorsubstrate 300 or a silicon layer or silicon germanium layer formed onthe semiconductor substrate 300 in the form of a crystalline phase or anamorphous phase.

[0058] Then, a first layer 304 of a metal which is one selected from thegroup consisting of cobalt (Co), titanium (Ti), tungsten (W), nickel(Ni), platinum (Pt), hafnium (Hf), and palladium (Pd) is deposited onthe contact hole 303 and the insulation layer 302 to a thickness ofgreater than 50 Å. As a result, a silicidation reaction between themetal and the silicon occurs at the bottom of the contact hole 303, sothat a native metal silicide layer 306 of a first phase is formed to athickness between about 25-35 Å.

[0059] Referring to FIG. 4B, the first layer 304 is selectively removedwhile retaining the native metal silicide layer 306 of the first phaseby a wet etching process using a chemical having an etching selectivitywith respect to the first layer 304 and the metal silicide layer 306.Preferably, in the wet etching process, a pan strip is carried out at atemperature of about 65° C. for about 30 minutes without using H₂O₂, ora sulfuric strip is carried out at a temperature of about 145° C. forabout 20 minutes.

[0060] Referring to FIG. 4C, a second layer 308 comprising titaniumnitride (TiN) is deposited on the metal silicide layer 306 of the firstphase and the insulation layer 302. Then, a rapid thermal process (RTP)is carried out at a temperature of about 850° C. for about 30 seconds inorder to cause a reaction between the metal silicide layer 306 of thefirst phase and the silicon, thereby transforming the metal silicidelayer 306 into a metal silicide layer 307 having a second phase whichhas a first stoichiometrical composition ratio different from a secondstoichiometrical composition ratio of the first phase. The second layer308 can be made of metallic material instead of titanium nitride (TiN).The second layer 308 acts as a diffusion barrier layer.

[0061] Next, a third layer 310 consisting of metal is deposited on thesecond layer 308 to bury the contact hole 303. As a result, an ohmiccontact structure consisting of the third layer 310—metal silicide layer307—semiconductor substrate 300 is obtained.

[0062] According to the third embodiment of the present invention, a lowresistance metal silicide having a high phase stability can be formed byusing a native metal silicide thin film formed at an interfacial surfacebetween a metal layer and a silicon area. Therefore, the metal silicidemakes direct contact with the silicon substrate so that an ohmic contactis formed, thereby reducing the contact resistance.

Fourth Embodiment of the Inventive Method

[0063]FIGS. 5A to 5D are sectional views of a semiconductor deviceshowing a method for forming a metal silicide layer in a semiconductordevice according to a fourth embodiment of the present invention.

[0064] Referring to FIG. 5A, a semiconductor substrate 400 consisting ofsilicon (Si), silicon germanium (SiGe) and silicon-on-insulator (SOI),or silicon-germanium-on-insulator (SGOI) is subject to an isolationprocess so that the semiconductor substrate 400 is divided into anactive area and a field area. Then, a gate oxide film 402 is grown onthe semiconductor substrate 400 by means of a thermal oxidation process.Then, a semiconductor material layer, such as a silicon layer or asilicon germanium layer in the form of a crystalline phase or anamorphous phase is deposited on the gate oxide film 402. Thesemiconductor material layer is patterned by using a photo etchingprocess so that a gate structure 404 is formed. Preferably, the gatestructure 404 is formed as a highly-impurity doped polycrystallinesilicon layer by means of a doping process, such as a diffusing process,an ion implanting process, or an in-situ doping process. In addition,when it is required to form the metal suicide layer only in thesource/drain area, a capping insulation layer (not shown) is stacked onan upper surface of the gate structure 404.

[0065] Then, after forming gate sidewall spacers 406 made of siliconoxide film at both sides of the gate stack 404, a source/drain area 408is formed on the active area of the semiconductor substrate 400 by usingan ion implantation process. In addition, it is possible to form alightly-doped source/drain area 405 aligned on the gate stack 404 byusing the ion implantation process before the gate sidewall spacers 404are formed on the gate stack 404.

[0066] Thereafter, a cleaning process is carried out to removeimpurities including particles remaining on the semiconductor substrate400 and a native oxide film created on a surface of the silicon area.Then the semiconductor substrate 400 is conveyed into an RF sputteringchamber. In order to prevent recreation of the native oxide film whilethe semiconductor substrate 400 is being conveyed, a cobalt layer 410 isdeposited in-situ, after performing the RF plasma etching process, onthe gate stack 404, the gate sidewall spacers 406, and the semiconductorsubstrate 400, to a thickness of about 100 Å. At this time, one oftitanium (Ti), tungsten (W), nickel (Ni), platinum (PT), hafnium (Hf),and palladium (Pd) may be selectively used instead of cobalt (Co).

[0067] As the cobalt layer 410 is deposited, the silicidation reactionbetween silicon and cobalt is generated at an interfacial surface of theexposed silicon area and the cobalt layer 410 so that a cobalt silicidelayer of the first phase, that is, a cobalt monosilicide (CoSi) layer412, is uniformly formed on the upper surface of the gate stack 404 andthe upper surface of the source/drain area 408, to a thickness of about30 Å. At this time, the native silicide layer in the form of amonosilicide may not be achieved if another refractory metal is usedinstead of cobalt.

[0068] Referring to FIG. 5B, the cobalt layer 410 is selectively removedwhile retaining the cobalt monosilicide layer 412 by a wet etchingprocess using a chemical having an etching selectivity with respect tocobalt and silicide. Preferably, in the wet etching process, a pan stripis carried out at a temperature of about 65° C. for about 30 minuteswithout using H₂O₂, or a sulfuric strip is carried out at a temperatureof about 145° C. for about 20 minutes.

[0069] Referring to FIG. 5C, a first capping layer 414 is deposited onthe semiconductor substrate 400 including the cobalt monosilicide layer412. The first capping layer 414 is made of a metallic compound selectedfrom the group consisting of titanium nitride (TiN), titanium tungsten(TiW), tantalum nitride (TaN), and tungsten nitride (WN). In addition,the first capping layer 414 can be made of an insulation material, suchas SiN or SiON. The first capping layer 414 prevents the diffusing ofcobalt and controls the speed of the silicidation reaction when thefollowing heat treatment process is carried out.

[0070] Referring to FIG. 5D, a rapid thermal process (RTP) is carriedout at a temperature of about 850° C. for about 30 seconds to cause areaction between metal silicide and silicon, thereby transforming thephase of the cobalt monosilicide layer 412 into a cobalt disilicide(CoSi₂) layer 415 having a thickness of less than about 100 Å and asheet resistance of about 20 Ω/

. At this time, if another refractory metal is used instead of cobalt,the resulting silicide layer may not be formed in a monosilicide phase.

[0071] After removing the first capping layer 414, an insulationmaterial having an etching selectivity with respect to the cobaltdisilicide (CoSi₂) layer 415 is deposited on the resulting structure toform a second capping layer 416. Then a contact hole (not shown) forexposing the source/drain area 408 is formed by partially etching thesecond capping layer 416.

[0072] According to the fourth embodiment of the present invention, auniform and thin metal silicide layer can be obtained by using thenative silicidation reaction generated at an interfacial area of metaland silicon. In addition, unlike the conventional silicide formingmethod, which requires performing the heat treatment process twice toobtain the stable silicide layer, the present invention can obtain thelow resistance metal silicide layer with high phase stability byperforming the heat treatment process only once. Accordingly, the heatbudget is reduced so that the shallow junction can be effectivelyachieved. Furthermore, according to the present invention, the processis simplified and reproducibility is improved and thereby makes massproduction possible.

[0073] In sum, the present invention allows a low resistance metalsilicide layer with high phase stability to be obtained by causing areaction between the native metal silicide layer of the first phase andsilicon by means of the heat treatment process in order that a thinmetal silicide layer can be uniformly formed. Also, since the presentinvention uses the native metal silicide layer, the step differenceportion can be uniformly coated.

[0074] Furthermore, since the present invention does not requireperforming the heat treatment process twice, the heat budget is reduced.Accordingly, when the present invention is applied to a salicidationprocess, a shallow junction is effectively obtained while the process issimplified.

[0075] Preferred embodiments of the present invention have beendisclosed herein and, although specific terms are employed, they areused and are to be interpreted in a generic and descriptive sense onlyand not for the purpose of limitation. Accordingly, it will beunderstood by those of ordinary skill in the art that various changes inform and scope may be made without departing from the spirit and scopeof the invention as set forth in the following claims.

1. A semiconductor device having a metal silicide contact structure, comprising: a substrate; an insulation layer having an opening formed on the substrate; a metal silicide layer formed in the opening of the insulation layer; and a conductive layer formed on the metal silicide layer, wherein the metal silicide layer is formed between the substrate and the conductive layer and the metal silicide layer has a thickness of less than about 100 Å.
 2. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the conductive layer is a semiconductor layer.
 3. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the metal silicide layer is formed using a native metal silicide having a first phase and a second phase, the second phase having a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase.
 4. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the substrate is comprised of a material selected from the group consisting of silicon, silicon germanium, silicon-on-insulator (SOI), and silicon-germanium-on-insulator (SGOI).
 5. A semiconductor device having a metal silicide contact structure as claimed in claim 1, further comprising a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase formed on the substrate.
 6. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the conductive layer comprises a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase.
 7. A semiconductor device having a metal suicide contact structure as claimed in claim 1, wherein the conductive layer is doped polycrystalline silicon.
 8. A semiconductor device having al metal silicide contact structure as claimed in claim 1, wherein the metal silicide layer has a resistance between about 3 to 20 Ω/□.
 9. A semiconductor device having a metal silicide contact structure as claimed in claim 1, further comprising a gate oxide film formed on the substrate.
 10. A semiconductor device having a metal silicide contact structure as claimed in claim 9, further comprising a gate stack formed on the gate oxide film.
 11. A semiconductor device having a metal silicide contact structure as claimed in claim 10, further comprising gate sidewall spacers formed on the sides of the gate stack.
 12. A semiconductor device having a metal silicide contact structure as claimed in claim 9, further comprising a source/drain area formed on the substrate exposed by the opening in the insulation layer.
 13. A semiconductor device having a metal silicide contact structure as claimed in claim 1, further comprising: field oxide films formed on the substrate; and a pad layer formed between the field oxide films and below the metal silicide layer.
 14. A semiconductor device having a metal silicide contact structure as claimed in claim 13, and further comprising: a second insulation layer formed above the field oxide films and the pad layer; a bit line stack formed on the second insulation layer; and a third insulation layer formed on the bit line stack and the second insulation layer.
 15. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the conductive layer is titanium nitride (TiN).
 16. A semiconductor device having a metal silicide contact structure as claimed in claim 1, wherein the conductive layer is a metallic material.
 17. A semiconductor device having a metal silicide contact structure as claimed in claim 15, further comprising a metal layer formed on the conductive layer.
 18. A semiconductor device having a metal silicide contact structure, comprising: a substrate; a gate oxide film formed on the substrate; a gate stack formed on the gate oxide film; a metal silicide layer formed on the substrate and the gate stack; and a capping layer formed above the metal silicide layer, wherein the metal silicide layer has a thickness less than about 100 Å.
 19. A semiconductor device having a metal silicide contact structure as claimed in claim 18, further comprising: a source/drain area formed on the substrate; a lightly-doped source/drain area formed on the substrate between the metal silicide layer formed on the substrate and the gate oxide film; and gate sidewall spacers formed on sides of the gate stack. 20-43. (Cancelled) 